The present invention relates to the field of data processing systems and more particularly to scan apparatus for accessing locations in the data processing system to facilitate testing and diagnostics. In the prior art, scan-in and scan-out (scan) has been accomplished by a number of approaches.
One approach connects the internal latches into a shift register. The shift register is formed using the machine latches which are used for normal processing. Such systems have not supported scan (scan-in or scan-out) of memory elements, and have not preserved the original content of latches during scan-out.
Another approach connects many internal data locations to a large multiplexor. With a large multiplexor, the internal data locations are accessible in parallel independently of the normal data paths of the system. However, with a multiplexor, the parallel scan approach has used an excessive number of chip inputs and outputs.
One prior art data processing system that has included scan capabilities is described in U.S. Pat. No. 4,244,019 entitled "Data Processing System Including A Program-Executing Secondary System Controlling A Program-Executing Primary System" assigned to the same assignee as the present invention.
The U.S. Pat. No. 4,244,019 patent provides a mechanism for scan of designed locations within a data processing system, independently of the normal data paths of that system. The scan techniques described in that patent have proved very useful. However, for data processing systems with greater chip densities, there is a need for more powerful scan apparatus which is more flexible and capable of more complex operations.
In accordance with the above background, there is a need for an improved scan apparatus for use in data processing systems.